Qwen2.5-Coder 32B Instruct on a GeForce RTX 5090
Yes, quantized. Q6_K is the largest that fits, leaving room for 18k tokens of context.
Verdict
Q6_K
29.4 GiB usable of 32 GB
Weights (Q4_K_M)
18.5 GiB
61.0 GiB at FP16 · 32.8B params · 6 of 6 quant rows are measured files
KV cache
256.0 KiB per token at FP16
64 layers × 8 KV heads × 128 dimensions
Speed ceiling
62 tok/s
1792 GB/s ÷ bytes read per token
Every quant, against this card
Weight bytes are the size of the real published file wherever one exists — 6 of these6 rows are measured from bartowski/Qwen2.5-Coder-32B-Instruct-GGUF, the rest computed from the parameter count. Max context is what the KV cache can grow to in whatever memory the weights leave behind, capped at the 32k tokens this model was trained to address.
| Precision | Bits/weight | Weights | Source | Fits | Max context | Ceiling |
|---|---|---|---|---|---|---|
| FP16 / BF16 | 16.00 | 61.0 GiB | measured file | −31.6 GiB | — | 2.4 tok/s offloaded |
| Q8_0 | 8.50 | 32.4 GiB | measured file | −3.0 GiB | — | 13.0 tok/s offloaded |
| Q6_K | 6.56 | 25.0 GiB | measured file | yes | 18,023 | 62 tok/s |
| Q5_K_M | 5.68 | 21.7 GiB | measured file | yes | 31,848 | 71 tok/s |
| Q4_K_M | 4.85 | 18.5 GiB | measured file | yes | 32,768 (model cap) | 81 tok/s |
| Q3_K_M | 3.89 | 14.8 GiB | measured file | yes | 32,768 (model cap) | 99 tok/s |
What the context actually costs
The KV cache is 2 · layers · kv_heads · head_dim bytes per token per element — 2 · 64 · 8 · 128 · 2 B = 256.0 KiB. It depends on the key/value head count, not the attention-head count and not the parameter count. This model shares 8 KV heads across 40 query heads, which divides the cache by 5 against multi-head attention.
| Context | KV cache (FP16) | KV cache (8-bit) | Plus Q4_K_M weights |
|---|---|---|---|
| 4,096 | 1.0 GiB | 512 MiB | 19.5 GiB |
| 8,192 | 2.0 GiB | 1.0 GiB | 20.5 GiB |
| 32,768 | 8.0 GiB | 4.0 GiB | 26.5 GiB |
The speed ceiling, and where it comes from
Generating one token reads every active weight from memory once. At Q6_K that is 25.0 GiB, plus a pass over the KV cache. A GeForce RTX 5090 moves 1792 GB/s (512-bit × 28 Gbps), so the arithmetic ceiling is 62 tok/s. Treat it as a bound, not an estimate: attention overhead, kernel launches and imperfect memory access keep real runtimes at roughly 60–80% of it, and nothing pushes past it.
Where these numbers come from
The model
- Parameters
- 32,763,876,352
- Layers
- 64
- Attention / KV heads
- 40 / 8
- Head dimension
- 128
- Trained context
- 32,768
- Checkpoint as published
- 61.0 GiB
Read from Qwen/Qwen2.5-Coder-32B-Instruct. The parameter count is the Hub's own total over the tensor shapes, not a figure taken from the model's name.
The accelerator
- Memory
- 32 GB GDDR7
- Bandwidth
- 1792 GB/s
- Bus
- 512-bit × 28 Gbps
- Assumed usable
- 92% → 29.4 GiB
Capacity and bandwidth from the vendor's specification. The bandwidth figure is checked against the bus width and data rate it derives from. The usable fraction is an assumption, not a spec: a driver context, compute workspace and any attached display come out of the same pool before a weight is loaded.
Questions this pairing answers
How much VRAM does Qwen2.5-Coder 32B Instruct need?
61.0 GiB for the weights at FP16 — 32.8B parameters at two bytes each — and 18.5 GiB at Q4_K_M. The KV cache is on top of that and is not a fixed number: this model spends 256.0 KiB per token of context, so 8,192 tokens costs a further 2.0 GiB. A GeForce RTX 5090 makes 29.4 GiB of its 32 GB available on the assumption below.
Can a GeForce RTX 5090 run Qwen2.5-Coder 32B Instruct?
Yes, quantized. Q6_K is the largest that fits, leaving room for 18k tokens of context. That is the weights and the KV cache together, against 29.4 GiB of usable memory.
How fast will Qwen2.5-Coder 32B Instruct run on a GeForce RTX 5090?
No faster than 62 tokens/second at Q6_K, and in practice below it. Decoding is memory-bound: every token reads all 25.0 GiB of weights plus the cache, and this card moves 1792 GB/s. That division is the ceiling — no kernel, runtime or driver beats it, and a real runtime typically reaches 60–80% of it.
Why does the context length change how much memory Qwen2.5-Coder 32B Instruct needs?
Because the KV cache holds one key and one value vector per token, per layer, for the whole conversation, and it is allocated separately from the weights. This model has 64 layers and 8 key/value heads of 128 dimensions, shared across 40 query heads — grouped-query attention, which divides the cache by 5. That works out at 256.0 KiB per token. Parameter count tells you nothing about this number.
The same model on a different card
- GeForce RTX 4090Q4_K_M
- GeForce RTX 3090Q4_K_M
- A100 40GB (SXM)Q8_0
- Radeon RX 7900 XTXQ4_K_M
- Apple M4 (24GB)Q3_K_M
- GeForce RTX 5080no fit
- GeForce RTX 5070 Tino fit
- GeForce RTX 4080 SUPERno fit
A different model on the same card
All 62 models on GeForce RTX 5090 →- DeepSeek-R1-Distill-Qwen 32BQ6_K
- Qwen2.5 32B InstructQ6_K
- QwQ 32BQ6_K
- Qwen3 32BQ6_K
- Laguna XS 2.1Q6_K
- Yi 1.5 34B ChatQ6_K
- KAT Coder V2.5 DevQ6_K
- Qwen AgentWorld 35B A3BQ6_K
Method and limits. Weight bytes are the byte size of the real published file wherever one exists, and the model's exact parameter count times the published llama.cpp bits-per-weight where it does not. That distinction is on every row above and it matters at both ends: a sub-1B model's Q4_K_M file runs a third larger than the nominal figure because k-quants keep its embedding tables at higher precision, and an already-4-bit release cannot be quantized upward at all. The KV cache is 2 · layers · kv_heads · head_dim · bytes per token, summed over layers with each sliding-window layer capped at its window. The speed figure is a roofline bound, not a benchmark: bandwidth divided by bytes read per token, which no runtime exceeds and every runtime falls short of. The usable fraction of card memory is an assumption: 92% here, which is what this lane assumes for a dedicated card — the other class assumes 75%, so it is not one number applied to every device. That is the only assumed input on this page; every other figure is computed from the model config and the card's published specification. Nothing on this page is written by a language model. Architecture from the model's published config, fetched 2026-08-07.