Qwen3 32B on an Apple M4 Pro (48GB)
Yes, quantized. Q8_0 is the largest that fits, leaving room for 14k tokens of context.
Verdict
Q8_0
36.0 GiB usable of 48 GB
Weights (Q4_K_M)
18.4 GiB
61.0 GiB at FP16 · 32.8B params · 1 of 6 quant rows are measured files
KV cache
256.0 KiB per token at FP16
64 layers × 8 KV heads × 128 dimensions
Speed ceiling
7 tok/s
273 GB/s ÷ bytes read per token
Every quant, against this card
Weight bytes are the size of the real published file wherever one exists — 1 of these6 rows are measured from the published checkpoint, the rest computed from the parameter count. Max context is what the KV cache can grow to in whatever memory the weights leave behind, capped at the 40k tokens this model was trained to address.
| Precision | Bits/weight | Weights | Source | Fits | Max context | Ceiling |
|---|---|---|---|---|---|---|
| FP16 / BF16 | 16.00 | 61.0 GiB | measured file | −25.0 GiB | — | 2.2 tok/s offloaded |
| Q8_0 | 8.50 | 32.4 GiB | nominal | yes | 14,667 | 7 tok/s |
| Q6_K | 6.56 | 25.0 GiB | nominal | yes | 40,960 (model cap) | 9 tok/s |
| Q5_K_M | 5.67 | 21.6 GiB | nominal | yes | 40,960 (model cap) | 11 tok/s |
| Q4_K_M | 4.83 | 18.4 GiB | nominal | yes | 40,960 (model cap) | 12 tok/s |
| Q3_K_M | 3.91 | 14.9 GiB | nominal | yes | 40,960 (model cap) | 15 tok/s |
What the context actually costs
The KV cache is 2 · layers · kv_heads · head_dim bytes per token per element — 2 · 64 · 8 · 128 · 2 B = 256.0 KiB. It depends on the key/value head count, not the attention-head count and not the parameter count. This model shares 8 KV heads across 64 query heads, which divides the cache by 8 against multi-head attention.
| Context | KV cache (FP16) | KV cache (8-bit) | Plus Q4_K_M weights |
|---|---|---|---|
| 4,096 | 1.0 GiB | 512 MiB | 19.4 GiB |
| 8,192 | 2.0 GiB | 1.0 GiB | 20.4 GiB |
| 32,768 | 8.0 GiB | 4.0 GiB | 26.4 GiB |
The speed ceiling, and where it comes from
Generating one token reads every active weight from memory once. At Q8_0 that is 32.4 GiB, plus a pass over the KV cache. An Apple M4 Pro (48GB) moves 273 GB/s, so the arithmetic ceiling is 7 tok/s. Treat it as a bound, not an estimate: attention overhead, kernel launches and imperfect memory access keep real runtimes at roughly 60–80% of it, and nothing pushes past it.
Where these numbers come from
The model
- Parameters
- 32,762,123,264
- Layers
- 64
- Attention / KV heads
- 64 / 8
- Head dimension
- 128
- Trained context
- 40,960
- Checkpoint as published
- 61.0 GiB
Read from Qwen/Qwen3-32B. The parameter count is the Hub's own total over the tensor shapes, not a figure taken from the model's name.
The accelerator
- Memory
- 48 GB LPDDR5X unified
- Bandwidth
- 273 GB/s
- Assumed usable
- 75% → 36.0 GiB
Capacity and bandwidth from the vendor's specification. The usable fraction is an assumption, not a spec: unified memory is shared with the OS and the display, and the GPU working-set cap is raisable on Apple silicon with `sudo sysctl iogpu.wired_limit_mb`.
Questions this pairing answers
How much VRAM does Qwen3 32B need?
61.0 GiB for the weights at FP16 — 32.8B parameters at two bytes each — and 18.4 GiB at Q4_K_M. The KV cache is on top of that and is not a fixed number: this model spends 256.0 KiB per token of context, so 8,192 tokens costs a further 2.0 GiB. An Apple M4 Pro (48GB) makes 36.0 GiB of its 48 GB available on the assumption below.
Can an Apple M4 Pro (48GB) run Qwen3 32B?
Yes, quantized. Q8_0 is the largest that fits, leaving room for 14k tokens of context. That is the weights and the KV cache together, against 36.0 GiB of usable memory.
How fast will Qwen3 32B run on an Apple M4 Pro (48GB)?
No faster than 7 tokens/second at Q8_0, and in practice below it. Decoding is memory-bound: every token reads all 32.4 GiB of weights plus the cache, and this card moves 273 GB/s. That division is the ceiling — no kernel, runtime or driver beats it, and a real runtime typically reaches 60–80% of it.
Why does the context length change how much memory Qwen3 32B needs?
Because the KV cache holds one key and one value vector per token, per layer, for the whole conversation, and it is allocated separately from the weights. This model has 64 layers and 8 key/value heads of 128 dimensions, shared across 64 query heads — grouped-query attention, which divides the cache by 8. That works out at 256.0 KiB per token. Parameter count tells you nothing about this number.
The same model on a different card
- RTX 6000 Ada GenerationQ8_0
- L40SQ8_0
- A100 40GB (SXM)Q8_0
- GeForce RTX 5090Q6_K
- Jetson AGX Orin (64GB)Q8_0
- GeForce RTX 4090Q4_K_M
- GeForce RTX 3090Q4_K_M
- Radeon RX 7900 XTXQ4_K_M
A different model on the same card
All 62 models on Apple M4 Pro (48GB) →- DeepSeek-R1-Distill-Qwen 32BQ8_0
- Qwen2.5 32B InstructQ8_0
- Qwen2.5-Coder 32B InstructQ8_0
- QwQ 32BQ8_0
- Laguna XS 2.1Q8_0
- Yi 1.5 34B ChatQ8_0
- KAT Coder V2.5 DevQ8_0
- Qwen AgentWorld 35B A3BQ8_0
Method and limits. Weight bytes are the byte size of the real published file wherever one exists, and the model's exact parameter count times the published llama.cpp bits-per-weight where it does not. That distinction is on every row above and it matters at both ends: a sub-1B model's Q4_K_M file runs a third larger than the nominal figure because k-quants keep its embedding tables at higher precision, and an already-4-bit release cannot be quantized upward at all. The KV cache is 2 · layers · kv_heads · head_dim · bytes per token, summed over layers with each sliding-window layer capped at its window. The speed figure is a roofline bound, not a benchmark: bandwidth divided by bytes read per token, which no runtime exceeds and every runtime falls short of. The usable fraction of card memory is an assumption: 75% here, which is what this lane assumes for unified memory, where the OS and window server share the same pool — the other class assumes 92%, so it is not one number applied to every device. That is the only assumed input on this page; every other figure is computed from the model config and the card's published specification. Nothing on this page is written by a language model. Architecture from the model's published config, fetched 2026-08-07.