Qwen2.5-Coder 32B Instruct on a Jetson Orin Nano Super (8GB)
No. Even Q3_K_M needs 14.8 GiB against 6.0 GiB usable.
Verdict
Does not fit
6.0 GiB usable of 8 GB
Weights (Q4_K_M)
18.5 GiB
61.0 GiB at FP16 · 32.8B params · 6 of 6 quant rows are measured files
KV cache
256.0 KiB per token at FP16
64 layers × 8 KV heads × 128 dimensions
Speed ceiling
5.2 tok/s
offloaded — nothing fits in device memory
Every quant, against this card
Weight bytes are the size of the real published file wherever one exists — 6 of these6 rows are measured from bartowski/Qwen2.5-Coder-32B-Instruct-GGUF, the rest computed from the parameter count. Max context is what the KV cache can grow to in whatever memory the weights leave behind, capped at the 32k tokens this model was trained to address.
| Precision | Bits/weight | Weights | Source | Fits | Max context | Ceiling |
|---|---|---|---|---|---|---|
| FP16 / BF16 | 16.00 | 61.0 GiB | measured file | −55.0 GiB | — | 1.3 tok/s offloaded |
| Q8_0 | 8.50 | 32.4 GiB | measured file | −26.4 GiB | — | 2.5 tok/s offloaded |
| Q6_K | 6.56 | 25.0 GiB | measured file | −19.0 GiB | — | 3.2 tok/s offloaded |
| Q5_K_M | 5.68 | 21.7 GiB | measured file | −15.7 GiB | — | 3.7 tok/s offloaded |
| Q4_K_M | 4.85 | 18.5 GiB | measured file | −12.5 GiB | — | 4.2 tok/s offloaded |
| Q3_K_M | 3.89 | 14.8 GiB | measured file | −8.8 GiB | — | 5.2 tok/s offloaded |
What the context actually costs
The KV cache is 2 · layers · kv_heads · head_dim bytes per token per element — 2 · 64 · 8 · 128 · 2 B = 256.0 KiB. It depends on the key/value head count, not the attention-head count and not the parameter count. This model shares 8 KV heads across 40 query heads, which divides the cache by 5 against multi-head attention.
| Context | KV cache (FP16) | KV cache (8-bit) | Plus Q4_K_M weights |
|---|---|---|---|
| 4,096 | 1.0 GiB | 512 MiB | 19.5 GiB |
| 8,192 | 2.0 GiB | 1.0 GiB | 20.5 GiB |
| 32,768 | 8.0 GiB | 4.0 GiB | 26.5 GiB |
What running it anyway would cost
Nothing here fits, so the weights would have to be split with part of the model in host RAM. At Q3_K_M that is 8.8 GiB on the host side, and assuming 90 GB/s of host memory bandwidth — a dual-channel DDR5 desktop — the ceiling falls to 5.2 tok/s, against 5.6 tok/s if the same weights were resident — 102 GB/s over the 18.08 GB one token reads, which is the weights the model routes through plus one pass over the cache, against a 15.94 GB weight file. That host bandwidth is an assumption and it is the number to change first if your machine differs; the ratio is the part that generalises.
Where these numbers come from
The model
- Parameters
- 32,763,876,352
- Layers
- 64
- Attention / KV heads
- 40 / 8
- Head dimension
- 128
- Trained context
- 32,768
- Checkpoint as published
- 61.0 GiB
Read from Qwen/Qwen2.5-Coder-32B-Instruct. The parameter count is the Hub's own total over the tensor shapes, not a figure taken from the model's name.
The accelerator
- Memory
- 8 GB LPDDR5 unified
- Bandwidth
- 102 GB/s
- Assumed usable
- 75% → 6.0 GiB
Capacity and bandwidth from the vendor's specification. The usable fraction is an assumption, not a spec: unified memory is shared with the OS and the display, and the GPU working-set cap is raisable on Apple silicon with `sudo sysctl iogpu.wired_limit_mb`.
Questions this pairing answers
How much VRAM does Qwen2.5-Coder 32B Instruct need?
61.0 GiB for the weights at FP16 — 32.8B parameters at two bytes each — and 18.5 GiB at Q4_K_M. The KV cache is on top of that and is not a fixed number: this model spends 256.0 KiB per token of context, so 8,192 tokens costs a further 2.0 GiB. A Jetson Orin Nano Super (8GB) makes 6.0 GiB of its 8 GB available on the assumption below.
Can a Jetson Orin Nano Super (8GB) run Qwen2.5-Coder 32B Instruct?
No. Even Q3_K_M needs 14.8 GiB against 6.0 GiB usable. Holding the smallest quant here would need a card with about 20 GB. Splitting the model across the PCIe bus is possible and slow — see the offload figure on this page.
How fast will Qwen2.5-Coder 32B Instruct run on a Jetson Orin Nano Super (8GB)?
It cannot run in this card's memory alone, so the speed is set by whatever bus the offloaded part is read across, not by the 102 GB/s of the card. At an assumed 90 GB/s of host memory bandwidth the ceiling is 5.2 tok/s at Q3_K_M, against 5.6 tok/s if it were resident — 102 GB/s over the 18.08 GB one token reads at Q3_K_M, priced at the 8k reference context. That is the weights the model routes through plus one pass over the cache, against a 15.94 GB weight file.
Why does the context length change how much memory Qwen2.5-Coder 32B Instruct needs?
Because the KV cache holds one key and one value vector per token, per layer, for the whole conversation, and it is allocated separately from the weights. This model has 64 layers and 8 key/value heads of 128 dimensions, shared across 40 query heads — grouped-query attention, which divides the cache by 5. That works out at 256.0 KiB per token. Parameter count tells you nothing about this number.
The same model on a different card
- GeForce RTX 3060 12GBno fit
- GeForce RTX 5080no fit
- GeForce RTX 5070 Tino fit
- GeForce RTX 4080 SUPERno fit
- GeForce RTX 4070 Ti SUPERno fit
- GeForce RTX 4060 Ti 16GBno fit
- GeForce RTX 4090Q4_K_M
- GeForce RTX 3090Q4_K_M
A different model on the same card
All 62 models on Jetson Orin Nano Super (8GB) →- DeepSeek-R1-Distill-Qwen 32Bno fit
- Qwen2.5 32B Instructno fit
- QwQ 32Bno fit
- Qwen3 32Bno fit
- Laguna XS 2.1no fit
- Yi 1.5 34B Chatno fit
- KAT Coder V2.5 Devno fit
- Qwen AgentWorld 35B A3Bno fit
Method and limits. Weight bytes are the byte size of the real published file wherever one exists, and the model's exact parameter count times the published llama.cpp bits-per-weight where it does not. That distinction is on every row above and it matters at both ends: a sub-1B model's Q4_K_M file runs a third larger than the nominal figure because k-quants keep its embedding tables at higher precision, and an already-4-bit release cannot be quantized upward at all. The KV cache is 2 · layers · kv_heads · head_dim · bytes per token, summed over layers with each sliding-window layer capped at its window. The speed figure is a roofline bound, not a benchmark: bandwidth divided by bytes read per token, which no runtime exceeds and every runtime falls short of. The usable fraction of card memory is an assumption: 75% here, which is what this lane assumes for unified memory, where the OS and window server share the same pool — the other class assumes 92%, so it is not one number applied to every device. Because nothing here fits, a second assumed input is in play — the 90 GB/s of host memory bandwidth the offload ceiling is priced at, stated above. Those two are the assumed inputs; every other figure is computed from the model config and the card's published specification. Nothing on this page is written by a language model. Architecture from the model's published config, fetched 2026-08-07.