Qwen2.5 72B Instruct on an H200 141GB (SXM)
Yes, quantized. Q8_0 is the largest that fits, leaving room for 32k tokens of context.
Verdict
Q8_0
129.7 GiB usable of 141 GB
Weights (Q4_K_M)
44.2 GiB
135.4 GiB at FP16 · 72.7B params · 6 of 6 quant rows are measured files
KV cache
320.0 KiB per token at FP16
80 layers × 8 KV heads × 128 dimensions
Speed ceiling
60 tok/s
4800 GB/s ÷ bytes read per token
Every quant, against this card
Weight bytes are the size of the real published file wherever one exists — 6 of these6 rows are measured from bartowski/Qwen2.5-72B-Instruct-GGUF, the rest computed from the parameter count. Max context is what the KV cache can grow to in whatever memory the weights leave behind, capped at the 32k tokens this model was trained to address.
| Precision | Bits/weight | Weights | Source | Fits | Max context | Ceiling |
|---|---|---|---|---|---|---|
| FP16 / BF16 | 16.00 | 135.4 GiB | measured file | −5.7 GiB | — | 7.9 tok/s offloaded |
| Q8_0 | 8.50 | 72.0 GiB | measured file | yes | 32,768 (model cap) | 60 tok/s |
| Q6_K | 7.08 | 59.9 GiB | measured file | yes | 32,768 (model cap) | 72 tok/s |
| Q5_K_M | 5.99 | 50.7 GiB | measured file | yes | 32,768 (model cap) | 84 tok/s |
| Q4_K_M | 5.22 | 44.2 GiB | measured file | yes | 32,768 (model cap) | 96 tok/s |
| Q3_K_M | 4.15 | 35.1 GiB | measured file | yes | 32,768 (model cap) | 119 tok/s |
What the context actually costs
The KV cache is 2 · layers · kv_heads · head_dim bytes per token per element — 2 · 80 · 8 · 128 · 2 B = 320.0 KiB. It depends on the key/value head count, not the attention-head count and not the parameter count. This model shares 8 KV heads across 64 query heads, which divides the cache by 8 against multi-head attention.
| Context | KV cache (FP16) | KV cache (8-bit) | Plus Q4_K_M weights |
|---|---|---|---|
| 4,096 | 1.3 GiB | 640 MiB | 45.4 GiB |
| 8,192 | 2.5 GiB | 1.3 GiB | 46.7 GiB |
| 32,768 | 10.0 GiB | 5.0 GiB | 54.2 GiB |
The speed ceiling, and where it comes from
Generating one token reads every active weight from memory once. At Q8_0 that is 72.0 GiB, plus a pass over the KV cache. An H200 141GB (SXM) moves 4800 GB/s, so the arithmetic ceiling is 60 tok/s. Treat it as a bound, not an estimate: attention overhead, kernel launches and imperfect memory access keep real runtimes at roughly 60–80% of it, and nothing pushes past it.
Where these numbers come from
The model
- Parameters
- 72,706,203,648
- Layers
- 80
- Attention / KV heads
- 64 / 8
- Head dimension
- 128
- Trained context
- 32,768
- Checkpoint as published
- 135.4 GiB
Read from Qwen/Qwen2.5-72B-Instruct. The parameter count is the Hub's own total over the tensor shapes, not a figure taken from the model's name.
The accelerator
- Memory
- 141 GB HBM3e
- Bandwidth
- 4800 GB/s
- Assumed usable
- 92% → 129.7 GiB
Capacity and bandwidth from the vendor's specification. The usable fraction is an assumption, not a spec: a driver context, compute workspace and any attached display come out of the same pool before a weight is loaded.
Questions this pairing answers
How much VRAM does Qwen2.5 72B Instruct need?
135.4 GiB for the weights at FP16 — 72.7B parameters at two bytes each — and 44.2 GiB at Q4_K_M. The KV cache is on top of that and is not a fixed number: this model spends 320.0 KiB per token of context, so 8,192 tokens costs a further 2.5 GiB. An H200 141GB (SXM) makes 129.7 GiB of its 141 GB available on the assumption below.
Can an H200 141GB (SXM) run Qwen2.5 72B Instruct?
Yes, quantized. Q8_0 is the largest that fits, leaving room for 32k tokens of context. That is the weights and the KV cache together, against 129.7 GiB of usable memory.
How fast will Qwen2.5 72B Instruct run on an H200 141GB (SXM)?
No faster than 60 tokens/second at Q8_0, and in practice below it. Decoding is memory-bound: every token reads all 72.0 GiB of weights plus the cache, and this card moves 4800 GB/s. That division is the ceiling — no kernel, runtime or driver beats it, and a real runtime typically reaches 60–80% of it.
Why does the context length change how much memory Qwen2.5 72B Instruct needs?
Because the KV cache holds one key and one value vector per token, per layer, for the whole conversation, and it is allocated separately from the weights. This model has 80 layers and 8 key/value heads of 128 dimensions, shared across 64 query heads — grouped-query attention, which divides the cache by 8. That works out at 320.0 KiB per token. Parameter count tells you nothing about this number.
The same model on a different card
- Apple M4 Max (128GB)Q8_0
- A100 80GB (SXM)Q8_0
- H100 80GB (SXM5)Q8_0
- Jetson AGX Orin (64GB)Q4_K_M
- RTX 6000 Ada GenerationQ3_K_M
- L40SQ3_K_M
- Apple M4 Pro (48GB)tight
- A100 40GB (SXM)Q3_K_M
A different model on the same card
All 62 models on H200 141GB (SXM) →- DeepSeek-R1-Distill-Llama 70BQ8_0
- Llama 3.1 70B InstructQ8_0
- Llama 3.1 Nemotron 70B InstructQ8_0
- Llama 3.3 70B InstructQ8_0
- Mixtral 8x7B InstructFP16 / BF16
- Hermes 4.3 36BFP16 / BF16
- KAT Coder V2.5 DevFP16 / BF16
- Qwen AgentWorld 35B A3BFP16 / BF16
Method and limits. Weight bytes are the byte size of the real published file wherever one exists, and the model's exact parameter count times the published llama.cpp bits-per-weight where it does not. That distinction is on every row above and it matters at both ends: a sub-1B model's Q4_K_M file runs a third larger than the nominal figure because k-quants keep its embedding tables at higher precision, and an already-4-bit release cannot be quantized upward at all. The KV cache is 2 · layers · kv_heads · head_dim · bytes per token, summed over layers with each sliding-window layer capped at its window. The speed figure is a roofline bound, not a benchmark: bandwidth divided by bytes read per token, which no runtime exceeds and every runtime falls short of. The usable fraction of card memory is an assumption: 92% here, which is what this lane assumes for a dedicated card — the other class assumes 75%, so it is not one number applied to every device. That is the only assumed input on this page; every other figure is computed from the model config and the card's published specification. Nothing on this page is written by a language model. Architecture from the model's published config, fetched 2026-08-07.