Qwen2.5 14B Instruct on an A100 80GB (SXM)
Yes — the unquantized weights fit with room for 32k tokens of context.
Verdict
Fits at FP16
73.6 GiB usable of 80 GB
Weights (Q4_K_M)
8.4 GiB
27.5 GiB at FP16 · 14.8B params · 6 of 6 quant rows are measured files
KV cache
192.0 KiB per token at FP16
48 layers × 8 KV heads × 128 dimensions
Speed ceiling
65 tok/s
2039 GB/s ÷ bytes read per token
Every quant, against this card
Weight bytes are the size of the real published file wherever one exists — 6 of these6 rows are measured from bartowski/Qwen2.5-14B-Instruct-GGUF, the rest computed from the parameter count. Max context is what the KV cache can grow to in whatever memory the weights leave behind, capped at the 32k tokens this model was trained to address.
| Precision | Bits/weight | Weights | Source | Fits | Max context | Ceiling |
|---|---|---|---|---|---|---|
| FP16 / BF16 | 16.00 | 27.5 GiB | measured file | yes | 32,768 (model cap) | 65 tok/s |
| Q8_0 | 8.50 | 14.6 GiB | measured file | yes | 32,768 (model cap) | 118 tok/s |
| Q6_K | 6.57 | 11.3 GiB | measured file | yes | 32,768 (model cap) | 148 tok/s |
| Q5_K_M | 5.69 | 9.8 GiB | measured file | yes | 32,768 (model cap) | 168 tok/s |
| Q4_K_M | 4.87 | 8.4 GiB | measured file | yes | 32,768 (model cap) | 192 tok/s |
| Q3_K_M | 3.98 | 6.8 GiB | measured file | yes | 32,768 (model cap) | 228 tok/s |
What the context actually costs
The KV cache is 2 · layers · kv_heads · head_dim bytes per token per element — 2 · 48 · 8 · 128 · 2 B = 192.0 KiB. It depends on the key/value head count, not the attention-head count and not the parameter count. This model shares 8 KV heads across 40 query heads, which divides the cache by 5 against multi-head attention.
| Context | KV cache (FP16) | KV cache (8-bit) | Plus Q4_K_M weights |
|---|---|---|---|
| 4,096 | 768 MiB | 384 MiB | 9.1 GiB |
| 8,192 | 1.5 GiB | 768 MiB | 9.9 GiB |
| 32,768 | 6.0 GiB | 3.0 GiB | 14.4 GiB |
The speed ceiling, and where it comes from
Generating one token reads every active weight from memory once. At FP16 / BF16 that is 27.5 GiB, plus a pass over the KV cache. An A100 80GB (SXM) moves 2039 GB/s, so the arithmetic ceiling is 65 tok/s. Treat it as a bound, not an estimate: attention overhead, kernel launches and imperfect memory access keep real runtimes at roughly 60–80% of it, and nothing pushes past it.
Where these numbers come from
The model
- Parameters
- 14,770,033,664
- Layers
- 48
- Attention / KV heads
- 40 / 8
- Head dimension
- 128
- Trained context
- 32,768
- Checkpoint as published
- 27.5 GiB
Read from Qwen/Qwen2.5-14B-Instruct. The parameter count is the Hub's own total over the tensor shapes, not a figure taken from the model's name.
The accelerator
- Memory
- 80 GB HBM2e
- Bandwidth
- 2039 GB/s
- Assumed usable
- 92% → 73.6 GiB
Capacity and bandwidth from the vendor's specification. The usable fraction is an assumption, not a spec: a driver context, compute workspace and any attached display come out of the same pool before a weight is loaded.
Questions this pairing answers
How much VRAM does Qwen2.5 14B Instruct need?
27.5 GiB for the weights at FP16 — 14.8B parameters at two bytes each — and 8.4 GiB at Q4_K_M. The KV cache is on top of that and is not a fixed number: this model spends 192.0 KiB per token of context, so 8,192 tokens costs a further 1.5 GiB. An A100 80GB (SXM) makes 73.6 GiB of its 80 GB available on the assumption below.
Can an A100 80GB (SXM) run Qwen2.5 14B Instruct?
Yes — the unquantized weights fit with room for 32k tokens of context. That is the weights and the KV cache together, against 73.6 GiB of usable memory.
How fast will Qwen2.5 14B Instruct run on an A100 80GB (SXM)?
No faster than 65 tokens/second at FP16 / BF16, and in practice below it. Decoding is memory-bound: every token reads all 27.5 GiB of weights plus the cache, and this card moves 2039 GB/s. That division is the ceiling — no kernel, runtime or driver beats it, and a real runtime typically reaches 60–80% of it.
Why does the context length change how much memory Qwen2.5 14B Instruct needs?
Because the KV cache holds one key and one value vector per token, per layer, for the whole conversation, and it is allocated separately from the weights. This model has 48 layers and 8 key/value heads of 128 dimensions, shared across 40 query heads — grouped-query attention, which divides the cache by 5. That works out at 192.0 KiB per token. Parameter count tells you nothing about this number.
The same model on a different card
- H100 80GB (SXM5)FP16 / BF16
- Jetson AGX Orin (64GB)FP16 / BF16
- RTX 6000 Ada GenerationFP16 / BF16
- L40SFP16 / BF16
- Apple M4 Pro (48GB)FP16 / BF16
- A100 40GB (SXM)FP16 / BF16
- GeForce RTX 5090FP16 / BF16
- Apple M4 Max (128GB)FP16 / BF16
A different model on the same card
All 62 models on A100 80GB (SXM) →- DeepSeek-R1-Distill-Qwen 14BFP16 / BF16
- Qwen3 14BFP16 / BF16
- Phi-4 14BFP16 / BF16
- OLMo 2 13B InstructFP16 / BF16
- Mistral Nemo 12B InstructFP16 / BF16
- Gemma 3 12B InstructFP16 / BF16
- Qwythos 9B Claude Mythos 5 1MFP16 / BF16
- Gemma 2 9B InstructFP16 / BF16
Method and limits. Weight bytes are the byte size of the real published file wherever one exists, and the model's exact parameter count times the published llama.cpp bits-per-weight where it does not. That distinction is on every row above and it matters at both ends: a sub-1B model's Q4_K_M file runs a third larger than the nominal figure because k-quants keep its embedding tables at higher precision, and an already-4-bit release cannot be quantized upward at all. The KV cache is 2 · layers · kv_heads · head_dim · bytes per token, summed over layers with each sliding-window layer capped at its window. The speed figure is a roofline bound, not a benchmark: bandwidth divided by bytes read per token, which no runtime exceeds and every runtime falls short of. The usable fraction of card memory is an assumption: 92% here, which is what this lane assumes for a dedicated card — the other class assumes 75%, so it is not one number applied to every device. That is the only assumed input on this page; every other figure is computed from the model config and the card's published specification. Nothing on this page is written by a language model. Architecture from the model's published config, fetched 2026-08-07.