Mistral 7B Instruct v0.3 on an RTX 6000 Ada Generation
Yes — the unquantized weights fit with room for 32k tokens of context.
Verdict
Fits at FP16
44.2 GiB usable of 48 GB
Weights (Q4_K_M)
4.1 GiB
13.5 GiB at FP16 · 7.2B params · 6 of 6 quant rows are measured files
KV cache
128.0 KiB per token at FP16
32 layers × 8 KV heads × 128 dimensions
Speed ceiling
62 tok/s
960 GB/s ÷ bytes read per token
Every quant, against this card
Weight bytes are the size of the real published file wherever one exists — 6 of these6 rows are measured from bartowski/Mistral-7B-Instruct-v0.3-GGUF, the rest computed from the parameter count. Max context is what the KV cache can grow to in whatever memory the weights leave behind, capped at the 32k tokens this model was trained to address.
| Precision | Bits/weight | Weights | Source | Fits | Max context | Ceiling |
|---|---|---|---|---|---|---|
| FP16 / BF16 | 16.00 | 13.5 GiB | measured file | yes | 32,768 (model cap) | 62 tok/s |
| Q8_0 | 8.50 | 7.2 GiB | measured file | yes | 32,768 (model cap) | 109 tok/s |
| Q6_K | 6.56 | 5.5 GiB | measured file | yes | 32,768 (model cap) | 137 tok/s |
| Q5_K_M | 5.67 | 4.8 GiB | measured file | yes | 32,768 (model cap) | 155 tok/s |
| Q4_K_M | 4.83 | 4.1 GiB | measured file | yes | 32,768 (model cap) | 176 tok/s |
| Q3_K_M | 3.89 | 3.3 GiB | measured file | yes | 32,768 (model cap) | 209 tok/s |
What the context actually costs
The KV cache is 2 · layers · kv_heads · head_dim bytes per token per element — 2 · 32 · 8 · 128 · 2 B = 128.0 KiB. It depends on the key/value head count, not the attention-head count and not the parameter count. This model shares 8 KV heads across 32 query heads, which divides the cache by 4 against multi-head attention.
| Context | KV cache (FP16) | KV cache (8-bit) | Plus Q4_K_M weights |
|---|---|---|---|
| 4,096 | 512 MiB | 256 MiB | 4.6 GiB |
| 8,192 | 1.0 GiB | 512 MiB | 5.1 GiB |
| 32,768 | 4.0 GiB | 2.0 GiB | 8.1 GiB |
The speed ceiling, and where it comes from
Generating one token reads every active weight from memory once. At FP16 / BF16 that is 13.5 GiB, plus a pass over the KV cache. An RTX 6000 Ada Generation moves 960 GB/s (384-bit × 20 Gbps), so the arithmetic ceiling is 62 tok/s. Treat it as a bound, not an estimate: attention overhead, kernel launches and imperfect memory access keep real runtimes at roughly 60–80% of it, and nothing pushes past it.
Where these numbers come from
The model
- Parameters
- 7,248,023,552
- Layers
- 32
- Attention / KV heads
- 32 / 8
- Head dimension
- 128
- Trained context
- 32,768
- Checkpoint as published
- 13.5 GiB
Read from mistralai/Mistral-7B-Instruct-v0.3. The parameter count is the Hub's own total over the tensor shapes, not a figure taken from the model's name.
The accelerator
- Memory
- 48 GB GDDR6 ECC
- Bandwidth
- 960 GB/s
- Bus
- 384-bit × 20 Gbps
- Assumed usable
- 92% → 44.2 GiB
Capacity and bandwidth from the vendor's specification. The bandwidth figure is checked against the bus width and data rate it derives from. The usable fraction is an assumption, not a spec: a driver context, compute workspace and any attached display come out of the same pool before a weight is loaded.
Questions this pairing answers
How much VRAM does Mistral 7B Instruct v0.3 need?
13.5 GiB for the weights at FP16 — 7.2B parameters at two bytes each — and 4.1 GiB at Q4_K_M. The KV cache is on top of that and is not a fixed number: this model spends 128.0 KiB per token of context, so 8,192 tokens costs a further 1.0 GiB. An RTX 6000 Ada Generation makes 44.2 GiB of its 48 GB available on the assumption below.
Can an RTX 6000 Ada Generation run Mistral 7B Instruct v0.3?
Yes — the unquantized weights fit with room for 32k tokens of context. That is the weights and the KV cache together, against 44.2 GiB of usable memory.
How fast will Mistral 7B Instruct v0.3 run on an RTX 6000 Ada Generation?
No faster than 62 tokens/second at FP16 / BF16, and in practice below it. Decoding is memory-bound: every token reads all 13.5 GiB of weights plus the cache, and this card moves 960 GB/s. That division is the ceiling — no kernel, runtime or driver beats it, and a real runtime typically reaches 60–80% of it.
Why does the context length change how much memory Mistral 7B Instruct v0.3 needs?
Because the KV cache holds one key and one value vector per token, per layer, for the whole conversation, and it is allocated separately from the weights. This model has 32 layers and 8 key/value heads of 128 dimensions, shared across 32 query heads — grouped-query attention, which divides the cache by 4. That works out at 128.0 KiB per token. Parameter count tells you nothing about this number.
The same model on a different card
- L40SFP16 / BF16
- Apple M4 Pro (48GB)FP16 / BF16
- A100 40GB (SXM)FP16 / BF16
- GeForce RTX 5090FP16 / BF16
- Jetson AGX Orin (64GB)FP16 / BF16
- GeForce RTX 4090FP16 / BF16
- GeForce RTX 3090FP16 / BF16
- Radeon RX 7900 XTXFP16 / BF16
A different model on the same card
All 62 models on RTX 6000 Ada Generation →- Falcon3 7B InstructFP16 / BF16
- DeepSeek-R1-Distill-Qwen 7BFP16 / BF16
- Qwen2.5 7B InstructFP16 / BF16
- Qwen2.5-Coder 7B InstructFP16 / BF16
- DeepSeek-R1-Distill-Llama 8BFP16 / BF16
- Llama 3.1 8B InstructFP16 / BF16
- Granite 3.3 8B InstructFP16 / BF16
- Qwen3 8BFP16 / BF16
Method and limits. Weight bytes are the byte size of the real published file wherever one exists, and the model's exact parameter count times the published llama.cpp bits-per-weight where it does not. That distinction is on every row above and it matters at both ends: a sub-1B model's Q4_K_M file runs a third larger than the nominal figure because k-quants keep its embedding tables at higher precision, and an already-4-bit release cannot be quantized upward at all. The KV cache is 2 · layers · kv_heads · head_dim · bytes per token, summed over layers with each sliding-window layer capped at its window. The speed figure is a roofline bound, not a benchmark: bandwidth divided by bytes read per token, which no runtime exceeds and every runtime falls short of. The usable fraction of card memory is an assumption: 92% here, which is what this lane assumes for a dedicated card — the other class assumes 75%, so it is not one number applied to every device. That is the only assumed input on this page; every other figure is computed from the model config and the card's published specification. Nothing on this page is written by a language model. Architecture from the model's published config, fetched 2026-08-07.