Computed

Laguna S 2.1 on an H100 80GB (SXM5)

Yes, quantized. Q4_K_M is the largest that fits, leaving room for 143k tokens of context.

Change the numbers →Laguna S 2.1 on every card H100 80GB (SXM5) across every model

Verdict

Q4_K_M

73.6 GiB usable of 80 GB

Weights (Q4_K_M)

66.8 GiB

219.0 GiB at FP16 · 117.6B params · 6 of 6 quant rows are measured files

KV cache

192.0 KiB per token at FP16

48 layers × 8 KV heads × 128 dimensions

Speed ceiling

685 tok/s

3350 GB/s ÷ bytes read per token

Every quant, against this card

Weight bytes are the size of the real published file wherever one exists — 6 of these6 rows are measured from bartowski/Laguna-S-2.1-GGUF, the rest computed from the parameter count. Max context is what the KV cache can grow to in whatever memory the weights leave behind, capped at the 1.0M tokens this model was trained to address.

Bars are the weight bytes at each precision; the dashed line is the usable memory of an H100 80GB (SXM5). Drawn from the computed byte counts, not sketched.

Precision	Bits/weight	Weights	Source	Fits	Max context	Ceiling
FP16 / BF16	16.00	219.0 GiB	measured file	−145.4 GiB	—	8.8 tok/s offloaded
Q8_0	8.51	116.4 GiB	measured file	−42.8 GiB	—	26.2 tok/s offloaded
Q6_K	6.92	94.7 GiB	measured file	−21.1 GiB	—	45.0 tok/s offloaded
Q5_K_M	5.72	78.2 GiB	measured file	−4.6 GiB	—	98.5 tok/s offloaded
Q4_K_M	4.88	66.8 GiB	measured file	yes	146,336	685 tok/s
Q3_K_M	3.68	50.3 GiB	measured file	yes	506,885	882 tok/s

What the context actually costs

The KV cache is 2 · layers · kv_heads · head_dim bytes per token per element — 2 · 48 · 8 · 128 · 2 B = 192.0 KiB. It depends on the key/value head count, not the attention-head count and not the parameter count. This model shares 8 KV heads across 48 query heads, which divides the cache by 6 against multi-head attention.

Sliding-window attention. 36 of this model's 48 layers attend to a 512-token window and stop growing there; only the remaining 12 keep scaling with context. That is why the cache figures below flatten out — and why a calculator that ignores the layer pattern over-states this model's long-context footprint several times over.

Context	KV cache (FP16)	KV cache (8-bit)	Plus Q4_K_M weights
4,096	264 MiB	132 MiB	67.1 GiB
8,192	456 MiB	228 MiB	67.3 GiB
32,768	1.6 GiB	804 MiB	68.4 GiB
131,072	6.1 GiB	3.0 GiB	72.9 GiB

The speed ceiling, and where it comes from

Generating one token reads every active weight from memory once. At Q4_K_M that is 4.1 GiB — only 6% of the checkpoint, because this is a mixture of experts and each token is routed to 10 of 256, plus a pass over the KV cache. An H100 80GB (SXM5) moves 3350 GB/s, so the arithmetic ceiling is 685 tok/s. Treat it as a bound, not an estimate: attention overhead, kernel launches and imperfect memory access keep real runtimes at roughly 60–80% of it, and nothing pushes past it.

Where these numbers come from

The model

Parameters: 117,561,977,600
Layers: 48
Attention / KV heads: 48 / 8
Head dimension: 128
Trained context: 1,048,576
Checkpoint as published: 219.0 GiB

Read from poolside/Laguna-S-2.1. The parameter count is the Hub's own total over the tensor shapes, not a figure taken from the model's name.

The accelerator

Memory: 80 GB HBM3
Bandwidth: 3350 GB/s
Assumed usable: 92% → 73.6 GiB

Capacity and bandwidth from the vendor's specification. The usable fraction is an assumption, not a spec: a driver context, compute workspace and any attached display come out of the same pool before a weight is loaded.

Questions this pairing answers

How much VRAM does Laguna S 2.1 need?

219.0 GiB for the weights at FP16 — 117.6B parameters at two bytes each — and 66.8 GiB at Q4_K_M. The KV cache is on top of that and is not a fixed number: this model spends 192.0 KiB per token of context on its full-attention layers, so 8,192 tokens costs a further 456 MiB. An H100 80GB (SXM5) makes 73.6 GiB of its 80 GB available on the assumption below.

Can an H100 80GB (SXM5) run Laguna S 2.1?

Yes, quantized. Q4_K_M is the largest that fits, leaving room for 143k tokens of context. That is the weights and the KV cache together, against 73.6 GiB of usable memory.

How fast will Laguna S 2.1 run on an H100 80GB (SXM5)?

No faster than 685 tokens/second at Q4_K_M, and in practice below it. Decoding is memory-bound: every token reads the 6% of weights this MoE routes to 4.1 GiB of weights plus the cache, and this card moves 3350 GB/s. That division is the ceiling — no kernel, runtime or driver beats it, and a real runtime typically reaches 60–80% of it.

Why does the context length change how much memory Laguna S 2.1 needs?

Because the KV cache holds one key and one value vector per token, per layer, for the whole conversation, and it is allocated separately from the weights. This model has 48 layers and 8 key/value heads of 128 dimensions, shared across 48 query heads — grouped-query attention, which divides the cache by 6. That works out at 192.0 KiB per token, except that 36 of the 48 layers use a 512-token sliding window and stop growing there. Parameter count tells you nothing about this number.

The same model on a different card

A different model on the same card

All 62 models on H100 80GB (SXM5) →

Method and limits. Weight bytes are the byte size of the real published file wherever one exists, and the model's exact parameter count times the published llama.cpp bits-per-weight where it does not. That distinction is on every row above and it matters at both ends: a sub-1B model's Q4_K_M file runs a third larger than the nominal figure because k-quants keep its embedding tables at higher precision, and an already-4-bit release cannot be quantized upward at all. The KV cache is 2 · layers · kv_heads · head_dim · bytes per token, summed over layers with each sliding-window layer capped at its window. The speed figure is a roofline bound, not a benchmark: bandwidth divided by bytes read per token, which no runtime exceeds and every runtime falls short of. The usable fraction of card memory is an assumption: 92% here, which is what this lane assumes for a dedicated card — the other class assumes 75%, so it is not one number applied to every device. That is the only assumed input on this page; every other figure is computed from the model config and the card's published specification. Nothing on this page is written by a language model. Architecture from the model's published config, fetched 2026-08-07.