FPGA Verilog Live Sculptor

// Mirrors src/lib/verilog-netlist.ts — the parser this page actually runs.
// The listing below is kept fragment-identical to the lib by
// verilog-netlist.test.ts; editing one without the other fails the suite.
// Tells `q <= d;` apart from the RELATIONAL <= in `if (a <= b)`,
// `for (i = 0; i <= 7; ...)` and `assign lt = a <= b;`. The regex this
// replaced matched any <= with a semicolon after it, so a purely
// combinational module reported registers it does not have.
export function countNonBlocking(src) {
  const statements = []; let depth = 0, start = 0;
  for (let i = 0; i < src.length; i++) {          // cut at ; / begin / end / else,
    const c = src[i];                             // but only at paren depth 0, so a
    if (c === '(') { depth++; continue; }         // for(...;...;...) header stays whole
    if (c === ')') { if (depth > 0) depth--; continue; }
    if (depth !== 0) continue;
    if (c === ';') { statements.push(src.slice(start, i)); start = i + 1; continue; }
    if (c === 'b' || c === 'e') {
      if (/[\w$]/.test(src[i - 1] ?? '')) continue;
      const kw = /^(?:begin|end|else)\b/.exec(src.slice(i, i + 6));
      if (!kw) continue;                          // endmodule / endcase fail \b
      statements.push(src.slice(start, i)); i += kw[0].length - 1; start = i + 1;
    }
  }
  statements.push(src.slice(start));
  let count = 0;
  for (const stmt of statements) {
    let d = 0;                        // no assign special case: lhs = rhs puts = first

    for (let i = 0; i < stmt.length; i++) {       // first depth-0 assignment op decides
      const c = stmt[i];
      if (c === '(') { d++; continue; }
      if (c === ')') { if (d > 0) d--; continue; }
      if (d !== 0) continue;
      if (c === '<' && stmt[i + 1] === '=') { count++; break; }
      if (c === '=' && stmt[i + 1] !== '=' && !'=!<>'.includes(stmt[i - 1] ?? '')) break;
    }
  }
  return count;
}

export function parseVerilogToNetlist(src, clkPeriod, routingSpread, jitter) {
  const noComments = src.replace(/\/\/.*$/gm,'').replace(/\/\*[\s\S]*?\*\//g,'');
  const modules = [...noComments.matchAll(/module\s+(\w+)/g)].map(m=>m[1]);
  const assigns = (noComments.match(/^\s*assign\s+/gm)||[]).length;
  const alwaysPos = (noComments.match(/always\s*@\s*\(\s*posedge/gi)||[]).length + (noComments.match(/always_ff\s*@/gi)||[]).length;
  const alwaysComb = (noComments.match(/always\s*@\s*\(\s*\*/g)||[]).length + (noComments.match(/always_comb/gi)||[]).length;
  const ops = (noComments.match(/[&|^]/g)||[]).length;
  const tildes = (noComments.match(/~/g)||[]).length;
  const addSub = (noComments.match(/(?<![=!<>])\+(?!\+)|(?<![=!<>])-(?!-)/g)||[]).length;
  // isolated * not part of ** and not the @(*) sensitivity star
  const noSensitivity = noComments.replace(/@\s*\(\s*\*\s*\)/g, '@ALL');
  const dsp = (noSensitivity.match(/(?<!\*)\*(?!\*)/g)||[]).length;
  const nb = countNonBlocking(noComments);
  const bram = (noComments.match(/reg\s*\[[^\]]+\]\s*\w+\s*\[[^\]]+\]|\bBRAM|\bRAMB|mem\[|memory/gi)||[]).length;
  const muxes = (noComments.match(/\bcase\b|\?\s*:/g)||[]).length;
  let luts = assigns + Math.ceil(ops * 0.35) + Math.ceil(tildes * 0.5) + Math.ceil(addSub * 0.55) + alwaysComb * 2 + muxes;
  if (luts === 0 && noComments.trim().length > 10) luts = 1;
  const regs = nb>0? nb : alwaysPos*2;
  const levels = Math.max(1, Math.ceil(Math.log2(Math.max(1,luts))*1.2 + assigns*0.15 + muxes * 0.25));
  const tLut=0.35, tRoute=0.12+routingSpread*0.45, tDsp=1.15, tCq=0.18, tSetup=0.08, tHold=0.05;
  const arrival = tCq + levels*(tLut+tRoute) + dsp*tDsp + bram*0.9;
  const required = clkPeriod - tSetup - jitter;
  const slack = required - arrival;
  const holdSlack = arrival*0.22 - 0.05;
  const fmax = 1000/(arrival + tSetup);
  return { modules, luts, regs, dsps:dsp, brams:bram, levels, arrival, required, slack, holdSlack, fmax };
}