Playground · research instrument
On-device AIAgentic Closed-Circuit Lab
Frontier 2026: Generative UI instruments, proposed by a local SLM (Phi-3 via WebGPU, private & zero-latency) and gated by a deterministic Zod → solver-registry circuit. The LLM sketches the experiment; Hammerstad-Jensen / RBJ / fitReport render the truth. No hallucinated numbers ever paint.
Independent research instrument — not claimed as MakerPortal shipped product code. Methods, equations, assumptions, and limitations are disclosed so you can inspect what the page does and does not establish.
Propose → Validate → Solve → Render
The stochastic half (LLM or heuristic) may only emit JSON inputs. The deterministic half — Zod + solver-registry — computes every number you see. A hallucinated Z0 = 900 Ω dies at the gate with a zod issue, never as a readout.
LLM proposes
JSON only
Zod gate
blocks hallucinations
Solver renders
deterministic bytes
Why this is frontier 2026
- Edge SLM: Phi-3-mini via
@mlc-ai/web-llm+ WebGPU — zero latency, private. - GenUI: LLM → instrument JSON (Tam bo/A2UI pattern), rendered as live readouts/Smith/eye.
- Machine Experience: GenUI JSON is also an MCP endpoint — same envelope agents consume.
- Tactile Brutalism: grain-noise + 1 px borders signal human instrumentation.
Proposal gate
idleNo proposal yet — type an intent and hit Propose.
Generated instrument cluster
GenUI JSON → livev1Validated readouts appear here. No solver, no pixels — this is the “closed circuit.”
Try: “50 Ω FR4” → validated Z₀, or “75+60j” → Smith.
Raw GenUI JSON (for agents / MCP)
SSR paints the empty shell (crawlable, no JS required). The island hydrates on client:visible. Pagefind indexes the shell; agents fetch the GenUI JSON via the MCP projection.
How the circuit holds — by construction
1 · Validator is SSOT
Zod schemas in circuit-schemas.ts restate solver-registry bounds. circuitSchemaIssues() fails the audit if they drift. A proposal that passes Zod but fails registry parse (off-grid tolerance) is still rejected.
2 · Solver is reference
runClosedCircuit calls envelopeFor(registryEntry, inputs) — the same object identity the strictEqual test guards. Biquad & LLM-VRAM lanes are provably the page function.
3 · GenUI is projection
A pure map solverEnvelope → GenUI JSON chooses instruments. The Astro renderer only knows instrument kinds (readout, smith, eye) — it cannot invent a number.
// The one rule: LLM proposes inputs, solver computes answers
import { z } from 'zod';
import { runClosedCircuit } from '../lib/circuit-engine.ts';
const raw = await llmPropose(intent); // JSON only, e.g. {W:0.3,H:0.2,Er:4.4,Zl:50}
const result = runClosedCircuit('si', raw, intent);
if (result.envelope.status === 'rejected') {
renderHallucinationBlocked(result.envelope.issues); // never rendered as data
} else {
// every pixel below comes from solver bytes, not LLM bytes
renderGenUI(result.genUI); // {version:1, instruments:[{kind:'readout', value:'49.8 Ω'}]}
showProvenance(result.envelope.solverUrl);
}Illustrative sketch: llmPropose, renderGenUI and renderHallucinationBlocked stand in for this page’s wiring. runClosedCircuit is real.
Gear behind the instruments this circuit drives
Stack · 4 picks
Hardware picks 4
$33.86BookHigh Speed Digital Design: A Handbook of Black Magic (Prentice Hall Modern Semiconductor Design)
Defines Hammerstad-Jensen Z0, skin depth delta=sqrt(2/ωμσ), and crosstalk K_b backward coupling — closed-form behind this lab's per-unit-length L,C extraction and NEXT/FEXT formulas.
$12.69DiagnosticHiLetgo USB Logic Analyzer Device with EMI Ferrite Ring USB Cable 24MHz 8CH 24MHz 8 Channel UART IIC SPI Debug
Budget 8-ch USB logic analyzer (sigrok/PulseView). Useful for RTOS GPIO timing and SI digital demos — not a Saleae substitute in bandwidth.
$89.99DiagnosticSEESII Upgraded NanoVNA-H4 Vector Network Analyzer, Latest V4.4 9KHz-1.5GHz HF VHF UHF 4" Touch Screen VNA Antenna Analyzer Measures S Parameters,Voltage Standing Wave Ratio, Phase,Delay, Smith Chart
Handheld VNA with touchscreen + SOL kit — S11/S21 lab companion for RF Bench and Antenna Sandbox.
$13.90KitAURSINC SMA Calibration Kit and SMA Male to Male Jumper for NanoVNA H H4 F V2 V3 SAA Mini1300 PS100 Vector Network Analyzer Antenna Analyzer
SOL cal standards + SMA jumper for NanoVNA H/H4 — SI Lab and RF Bench SOLT demos.
Prices shown were retrieved from the Amazon Product Advertising API on 19 July 2026 and are indicative only — the price and availability on Amazon at the time of purchase apply.
Questions a principal would ask
Does the LLM ever compute a result?
No. The LLM is a proposer only. It outputs JSON inputs (e.g., {W,H,Er,Zl} for Signal Integrity). Zod validates those inputs; then the deterministic Hammerstad-Jensen / RBJ / fitReport solver computes the answer. Invalid JSON is rejected and never rendered. This is the “closed circuit”: stochastic → deterministic gate → pixels.
WebLLM vs heuristic — which proposer am I using?
Out of the box the lab is interactive with zero download via a heuristic proposer (pattern-matches intent → valid JSON). Click “Load Phi-3 mini” to progressively enhance to an in-browser SLM via WebGPU (Phi-3-mini-4k ~2 GB, Gemma-2B alternative). The validator and solver are identical either way — only the proposer changes, so audit coverage is complete without the model.
What is GenUI here?
A declarative JSON instrument cluster versioned as v1: each validated proposal is mapped to a set of instruments (readout, smith, eye, response points, markdown). The renderer has no LLM branch — it only knows how to paint those instruments from solver bytes. That is A2UI/Tambo-style Generative UI adapted to hardware.’s constraint: generated UI but deterministic numbers.
How does this extend solver-registry?
Signal Integrity and RF Bench had no registry entry (inline math in .astro <script>). This lab extracts their closed forms into src/lib/circuit-engine.ts as pure functions and gates them with zod schemas that mirror registry parseInputs bounds. Biquad and LLM-VRAM lanes delegate to solver-registry directly via envelopeFor() — same function object, provable by strictEqual.
Will this pass CI gates?
Yes. src/lib/circuit-schemas.ts:95 exposes circuitSchemaIssues() for the audit suite; Astro SSR paints the shell only (no LLM in server bundle); the island is client:visible with dynamic import() so astro check and Pagefind indexing both ignore WebLLM.
Shareable still
The instrument, captured—not illustrated.
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